PHENIX Level-1 Trigger Board Schematics and Documentation

This web page contains documentation and schematics for the PHENIX Level-1 Trigger system. In addition to schematics and detailed design information, links to several talks and presentation on the general design of Level-1 are also included. All schematics are in Adobe PDF format.
 

Old Level-1 Website and Documentation

General Level-1 Talks and Presentations:

Manuals:

GL1 Operations Manual (getting out of date!)
 

Level-1 Trigger:

 PHENIX GL1 Talk at the IEEE NSS'98 Conference (Powerpoint)
 Proceedings from IEEE NSS'98 (PS file)

PHENIX Level-1 Trigger Talk at the IEEE RT'99 Conference (Powerpoint)
Proceedings from IEEE RT'99 (PDF file)
 

Level-1 Cabling and Crate Interconnects:

Level-1 Cu Cables and Pinouts

GTM to GL1 Box (BNL built)

GL1 Backplane Schematics
 

Global Level-1 Board 1P (GL1-1P):

GL1-1P Design Review Presentation

Board Level Schematics

VME Register Map

LUTMUX Chip

COUNT Chip

LUTCNTRL Chip

REGION Chip

FIFO Chip

MUX Chip

PRTNBUSY_XBAR Chip

XBAR Chip

XFRCNTRL Chip
 

Global Level-1 Board 1 (GL1-1):

GL1_SCALEDOWN Chip
 

Generic Local Level-1 Board (MuID, NTC/T0/ZDC):

MUID LL1 Design Specifications Document

MuID LL1 Initial Algorithm Description (by Vince Cianciolo)

Generic LL1 Board Level Schematics

Fiber Transmitter Test Board Schematics

MuID LL1 Xilinx Project Files (zipped):

muid_h1r1 Xilinx Project Files

muid_h2r1 Xilinx Project Files

muid_h3r1 Xilinx Project Files

muid_h4r1 Xilinx Project Files

muid_h5r1 Xilinx Project Files

muid_v1r1 Xilinx Project Files

muid_v2r1 Xilinx Project Files

muid_v3r1 Xilinx Project Files

muid_v4r1 Xilinx Project Files

muid_v5r1 Xilinx Project Files

muid_h_cntrlr1 Xilinx Project Files

muid_v_cntrlr1 Xilinx Project Files

MuID Symset Xilinx Project Files

MuID Edge Counter Xilinx Project Files

MuID Channel Mapping Xilinx Project Files

MuID MUX Chip Schematics:

MUMUX_16x6 Schematics Directory

Schematic Elements for muid_work chips:

MuID Schematics Directory

MuID Accepted Event Readout Format:

Horizontal and Control Chip Format

Vertical Chip Format
 

Beam-Beam Local Level-1:

Board Level Schematics (Board 2)
 

Transition Cards:

Reduced Bit Input Board II

Standard Transition Card, Rev. 1
 

Actel Logic Macros:

accum_32x4in

count_32a

fadd_32x4in

reg_32

bfrd_count32

count_4

count_3

mx16x32

xbar_32x1

count_mod15

mx2x32

z100ms_os

pos_edg_det

count_modulr_a (outdated)

count_modulr_b (w/timing adjust)
 

Problems? Contact lajoie@iastate.edu .

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